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MLX71121
300 to 930MHz FSK/FM/ASK Receiver Features
Dual RF input for antenna space and frequency diversity, LNA cascading or differential feeding Fully integrated PLL-based synthesizer 2nd mixer with image rejection Reception of ASK or FSK modulated signals Wide operating voltage and temperature ranges Very low standby current consumption Low operating current consumption Internal IF filter Internal FSK demodulator Average or peak detection data slicer mode RSSI output with high dynamic range for RF level indication Output noise cancellation filter MCU clock output High over-all frequency accuracy 32-pin Quad Flat No-Lead Package (QFN)
Ordering Information
Part Number MLX71121 Temperature Code K (-40 C to 125 C) Package Code LQ (32 L QFN 5x5 Quad) Delivery Form 73 pc/tube 5000 pc/T&R
Application Examples
General digital and analog RF receivers at 300 to 930MHz Tire pressure monitoring systems (TPMS) Remote keyless entry (RKE) Low power telemetry systems Alarm and security systems Active RFID tags Remote controls Garage door openers Home and building automation
LNASEL RFSEL
Pin Description
top
DTAO CLKO IFSEL ROI
bottom
LNAI1 VEE LNAO1 MIXP MIXN LNAO2 VEE LNAI2
MLX71121
RSSI CINT VCC PDN PDP SLC DFO DF1
General Description
The MLX71121 is a multi-band, single-channel/dual-channel RF receiver based on a double-conversion super-heterodyne architecture. It can receive FSK and ASK modulated signals. The IC is designed for general purpose applications for example in the European bands at 433MHz and 868MHz or for similar applications in North America or Asia, e.g. at 315MHz or 915MHz. The receiver's extended temperature and supply voltage ranges make the device a perfect fit for automotive or similar applications where harsh environmental conditions are expected.
39010 71121 Rev. 007
Page 1 of 28
VCC MIXO VEE IFAP IFAN MODSEL SLCSEL DF2
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver Document Content
1 Theory of Operation ...................................................................................................4
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 General ............................................................................................................................. 4 Technical Data Overview.................................................................................................. 4 Block Diagram .................................................................................................................. 5 Operating Modes .............................................................................................................. 6 LNA Selection ................................................................................................................... 6 Mixer Section .................................................................................................................... 7 IF Filter ............................................................................................................................. 7 IF Amplifier ....................................................................................................................... 7 PLL Synthesizer ............................................................................................................... 7 Reference Oscillator ......................................................................................................... 8 Clock Output..................................................................................................................... 8 FSK Demodulator ............................................................................................................. 8 Baseband Data Path ........................................................................................................ 9 Data Filter ....................................................................................................................... 10 Data Slicer ...................................................................................................................... 10
Averaging Detection Mode..................................................................................................... 11 Peak Detection Mode ............................................................................................................. 11
1.15.1 1.15.2
1.16
Data Output and Noise Cancellation Filter ..................................................................... 12
2
Functional Description ............................................................................................13
2.1 2.2 2.3 2.4 Frequency Planning........................................................................................................ 13 Calculation of Frequency Settings.................................................................................. 14 Standard Frequency Plans ............................................................................................. 15 433/868MHz Frequency Diversity .................................................................................. 15
3 4
Pin Definitions and Descriptions ............................................................................16 Technical Data..........................................................................................................20
4.1 4.2 4.3 4.4 4.5 Absolute Maximum Ratings ............................................................................................ 20 Normal Operating Conditions ......................................................................................... 20 DC Characteristics.......................................................................................................... 21 AC System Characteristics ............................................................................................. 22 External Components ..................................................................................................... 23
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
5 Test Circuits .............................................................................................................24
5.1
5.1.1
Dual-Channel Application Circuit.................................................................................... 24
Test Circuit Component List of Figures 11 ................................................................................ 25
6
Package Description ................................................................................................26
6.1 Soldering Information ..................................................................................................... 26
7 8 9
Reliability Information .............................................................................................27 ESD Precautions ......................................................................................................27 Disclaimer .................................................................................................................28
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 1
1.1
Theory of Operation
General
The MLX71121 receiver architecture is based on a double-conversion super-heterodyne approach. The two LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high degree of image rejection is provided even without using an RF front-end filter. At applications asking for very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA. The second mixer MIX2 is an image-reject mixer. The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion mixers (MIX1, MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data signal can be performed by a noise cancellation filter (NCF) building block. The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the RF signal differentially. A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize power dissipation. A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcontroller. The clock output is open drain and gets activated through a load connected to positive supply.
1.2
Technical Data Overview
Input frequency ranges: 300 to 470MHz 610 to 930MHz Power supply range: 2.1 to 5.5V Temperature range: -40 to +125C Shutdown current: 50 nA Operating current: 10.0 to 11.1mA FSK input sensitivity: -107dBm* (433MHz) ASK input sensitivity: -112dBm* (433MHz) Internal IF: 1.8MHz with 300kHz 3dB bandwidth FM/FSK deviation range: 10kHz to 100kHz Image rejection: st 65dB 1 IF (with external RF front-end filter) 25dB 2nd IF (internal image rejection) Maximum data rate: 50kps RZ (bi-phase) code, 100kps NRZ Spurious emission: < -54dBm Linear RSSI range: > 60dB Crystal reference frequency: 16 to 27MHz MCU clock frequency: 2.0 to 3.4MHz
* at 4kbps NRZ, BER = 310-3, without SAW front-end-filter loss
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.3 Block Diagram
IFSEL
RSSI
VCC
MODSEL
LNAO2
DF1
MIXO
MIXN
VEE
2
LNAO1
MIXP
VEE
100k
100k
DF2
3
6
4
5
9
10
11
12
13
27
24
14
17
16
ASK
OA1
SW1
100k 100k
DFO
18
LNAI1
1
LNA1 MIX1 MIX2 IFF IFA
FSK
LNASEL
32
PKDET+
20
LNAI2
8
LO1
LO2
LNA2 N1 counter VCO BIAS
ENRX
FSK DEMOD PFD RO
SW2
PDP
VEE
7
100k
PKDET_
PDN
21
RFSEL
31
SEQ
N2 counter
TEST
26
LF
CP
ROI
DIV 8
SLCSEL CLKO VCC SLC
OA2
NCF
DTAO
29
CINT
22 19 23
30
25
28
15
Fig. 1:
MLX71121 block diagram
The MLX71121 receiver IC consists of the following building blocks: * PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2. The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback divider chain (N1,N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a crystal-based reference oscillator (RO). Two low-noise amplifiers (LNA1, LNA2) for high-sensitivity RF signal reception First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency) Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF IF Filter (IFF) with a 1.8MHz center frequency and a 300kHz 3dB bandwidth IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output FSK demodulator (FSK DEMOD) Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively Positive (PKDET+) and negative (PKDET-) peak detectors Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak detection mode. Noise cancellation filter (NCF) Sequencer circuit (SEQ) and biasing (BIAS) circuit Clock output (DIV8)
* * * * * * * * * * * *
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.4 Operating Modes
The receiver offers two operating modes selectable by setting the corresponding logic level at pin ENRX. ENRX 0 1 Note: ENRX is pulled down internally. The receiver's start-up procedure is controlled by a sequencer circuit. It performs the sequential activation of the different building blocks. It also initiates the pre-charging of the data filter and data slicer capacitors in order to reduce the overall start-up time and current consumption during the start-up phase. At ENRX = 0, the receiver is in shutdown mode and draws only a few nA. The bias system and the reference oscillator are activated after enabling the receiver by a positive edge at pin ENRX. The crystal oscillator (RO) is turned on first. Then the crystal oscillation amplitude builds up from noise. After reaching a certain amplitude level at pin ROI, the whole IC is activated and draws the full receive mode current consumption ICC. This event is used to start the pre-charging of the external data path capacitors. Pre-charging is finished after 5504 clock cycles. After that time the data output pin DTAO output is activated. Description Shutdown mode Receive mode
ENRX
ICC I RO ISDN
DTAO
Hi-Z t on RO t on RX
Fig. 2:
valid data t SEQ
Hi-Z
Timing diagram of start-up and shutdown behavior
1.5
LNA Selection
The receiver features two identical LNAs. Each LNA is a cascode amplifier with a voltage gain of approximately 18dB. The actual gain depends on the antenna matching network at the inputs and the LC tank network between the LNA outputs and mixer input. LNA operation can be controlled by the LNASEL pin. LNASEL 0 Hi-Z 1 Description LNA1 active, LNA2 shutdown LNA1 and LNA2 active LNA1 shutdown, LNA2 active
Pin LNASEL is internally pulled to VCC/2 during receive mode. Therefore both LNAs are active if LNASEL is left floating (Hi-Z state).
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.6 Mixer Section
The mixer section consists of two mixers. Both are double-balanced mixers. The second mixer is built as an image rejection mixer. The first mixer's inputs (MIXP and MIXN) are functionally the same. For single-ended drive, the unused input has to be tied to ground via a capacitor. A soft band-pass filter is placed between the mixers. RFSEL 0 1 Description Input frequency range 300 to 470MHz Input frequency range 610 to 930MHz
Pin RFSEL is used to select the required RF band. The LO frequencies and the proper sidebands for image suppression will be set accordingly.
1.7
IF Filter
gain/dB 0 B 3dB
The MLX71121 comprises an internal IF filter with a -3dB bandwidth (B3dB) of 300kHz and a -40dB attenuation bandwidth (B40dB) of 1.4MHz. This filter contains three capacitively coupled biquad stages that represent resonant tanks at a filter center frequency (fcent) of 1.8MHz
-20 B 40dB -40
Fig. 3:
IF filter tolerance scheme
f cent f IF2
1.8
IF Amplifier
After having passed the IF filter, the signal is amplified by a high-gain limiting amplifier. It consists of several AC-coupled gain stages with a bandwidth of 400kHz to 11MHz. The overall small-signal pass-band gain is about 80dB. A received-signal-strength indicator (RSSI) signal is generated within the IF amplifier and is available at pin RSSI.
1.9
PLL Synthesizer
The PLL synthesizer consists of a fully integrated voltage-controlled oscillator running at 400MHz to 640MHz, a distributed feedback divider chain, an edge-triggered phase-frequency detector, a charge pump, a loop filter and a crystal-based reference oscillator. The PLL is used for generating the LO signals. The LO1 is directly taken from the VCO output, and the LO2 is derived from the LO1 signal passing the N1 counter. Another counter N2 follows N1. The overall feedback divider ratio Ntot is fixed to 24. The values of N1 and N2 are depending on the selected RF band that can be chosen via pin RFSEL. RFSEL 0 1 fLO1min [MHz] 400 400 fLO1max [MHz] 640 640 fLO2min [MHz] 100 200 fLO2max [MHz] 160 320 N1 4 2 N2 6 12 Ntot 24 24
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.10 Reference Oscillator
A Colpitts crystal oscillator with integrated functional capacitors is used as the reference oscillator (RO) of the PLL synthesizer. The equivalent input capacitance CRO offered to the crystal at pin ROI is about 18pF. The crystal oscillator features an amplitude control loop. This is to assure a very stable frequency over the specified supply voltage and temperature range together with a short start-up time. A buffer amplifier with hysteresis is between RO and PFD. Also a clock divider follows the buffer.
1.11 Clock Output
The clock output pin CKOUT is an open-drain output. For power saving reasons, the circuit is only active if an external pull-up resistor RCL is applied to the pin. Furthermore, RCL can be used to adjust the clock waveform. It forms an RC low-pass together with the capacitive load at the pin, the parasitics of the PCB and the input capacitance of the external circuitry (e.g. a microcontroller). The clock output feature is disabled if pin CKOUT is connected to ground or left open.
VCC
CLKO
RCL
RO output
DIV8
Control logic
CL
Fig. 4:
Clock output implementation
1.12 FSK Demodulator
The integrated FSK demodulator is based on a phase-coincidence demodulator principle. An injectionlocked oscillator (ILO) is used as a frequency-dependent phase shifter. This topology features a good linearity of the frequency-phase relationship over the entire locking range. The type of demodulator has no built-in constraints regarding the modulation index. It also offers a wide carrier acceptance range. In addition, the demodulator provides an AFC loop for correcting the remaining free-running frequency error and drift effects, and also to remove possible frequency offsets between transmitter and receiver frequencies. The AFC loop features a dead band which means that the AFC loop is only closed if the demodulator output voltage leaves the linear region of the demodulator. Most of the time, the control loop is open. This leads to several advantages. The AFC loop bandwidth can be high and therefore the reaction time is short. Furthermore the demodulator itself has no low-end cut-off frequency. The FSK demodulator has a negative control slope, this means the output voltage decreases by increasing the IF2 frequency. This guarantees an overall positive slope because the mixer section converts the receive frequency to IF2 either with high-low or low-high side injection. The FSK demodulator is turned off during ASK demodulation.
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.13 Baseband Data Path
The baseband data path can be divided into a data filter section and a data slicer section.
MODSEL DF1 DF2
ASK
100k 100k
data filter
SW1
FSK
OA1
DF0
PKDET+
data slicer
PDP
100k
S4
S1
100k
S2
switches
SLC
SLCSEL
S3
100k
VCC
PKDET _
S5
PDN
S6
Fig. 5:
OA2 Control logic
DTAO CINT
Block diagram of the data path
The data filter input is either connected to the ASK or to the FSK demodulation output. Pin MODSEL can be used to set the internal switch SW1 accordingly. MODSEL 0 1 Description ASK demodulation FSK demodulation
For ASK demodulation, the RSSI signal of the IFA is used. During FSK demodulation, SW1 is connected to the FSK demodulator output. The SLCSEL pin is used to control the internal switches depending on operating and slicer mode. Pins DF1, DF2, DFO, SLC and DTAO are left floating during shutdown mode. So they are in a high-Z state.
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.14 Data Filter
The data filter is formed by the operational amplifier OA1, two internal 100k resistors and two external capacitors. It is implemented as a 2nd order Sallen-Key filter. The low pass filter characteristic rejects noise at higher frequencies and therefore leads to an increased sensitivity.
CF1
DF1
CF2
DF2
data filter
100k 100k
OA1
DF0
Fig. 6:
Data filter
The filter's pole locations can be set by the external capacitors CF1 and CF2. The cut-off frequency fc has to be adjusted according to the transmission data rate R. It should be set to approximately 1.5 times the fastest expected data rate. For a Butterworth filter characteristic, the data filter capacitors can be calculated as follows.
CF1 =
1 2 100k f c
RNRZ [kbit/s] 1.2 2.4 3.2 4.8 6.6 9.6 12 fc [kHz] 0.9 1.8 2.4 3.6 5 7.2 9
CF2 =
CF1 2
RRZ [kbit/s] 0.6 1.2 1.6 2.4 3.3 4.8 6.0
CF1 [pF] 2200 1200 1000 680 470 330 220
CF2 [pF] 1000 680 470 330 220 150 100
1.15 Data Slicer
The purpose of the data slicer is to convert the filtered data signal into a digital output. It can therefore be considered as an analog-to-digital converter. This is done by using the operational amplifier OA2 as a comparator that compares the data filter output with a threshold voltage. The threshold voltage can be derived in two different ways from the data signal. SLCSEL 0 1 Description Averaging detection mode Peak detection mode
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.15.1 Averaging Detection Mode
PKDET+
The simplest configuration is the averaging or RC integration method. Here an on-chip 100k resistor together with an external slicer capacitor (CSL) are forming an RC low-pass filter. This way the threshold voltage automatically adjusts to the mean or average value of the analog input voltage. To create a stable threshold voltage, the cut-off frequency of the low pass has to be lower than the lowest signal frequency.
data slicer
PDP
100k
data filter
100k
S4
S1
SLC
S2
switches
SLCSEL
S3
100k
VCC
CSL
CSL
AVG 100k
AVG =
1.5 R RZ
PKDET _
S5
PDN
S6
A long string of zeros or ones, like in NRZ codes, can cause a drift of the threshold. That's why a Manchester or other DC-free coding scheme works best. The peak detectors are disabled during averaging detection mode, and the output pins PDP and PDN are pulled to ground (S4, S6 are closed).
OA2
Control logic
DTAO CINT
Fig. 7:
Data path in averaging detection mode
1.15.2
Peak Detection Mode
PKDET+
Peak detection mode has a general advantage over averaging detection mode because of the part attack and slow release times. Peak detection should be used for all non DC-free codes like NRZ. In this configuration the threshold is generated by using the positive and negative peak detectors. The slicer comparator threshold is set to the midpoint between the high output and the low output of the data filter by an on-chip resistance divider. Two external capacitors (CP1, CP2) determine the release times for the positive and negative envelope. The two on-chip resistors provide a path for the capacitors to discharge. This allows the peak detectors to dynamically follow peak changes of the data filter output voltage. The attack times are very short due to the high peak detector load currents of about 500uA. The decay time constant mainly depends on the longest time period without bit polarity change. This corresponds to the maximum number of consecutive bits with the same polarity (NMAX).
data slicer
100k
PDP
data filter
100k
S4
CP1
S1
VCC
S2
switches
SLC
SLCSEL
S3
100k
VCC
PKDET _
S5
PDN
CP2
S6
OA2
Control logic
DTAO CINT
Fig. 8:
Data path in peak detection mode
CP1/2 DECAY 100k
DECAY
N = MAX R NRZ
If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disabled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output of the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing of CP1 and CP2 during start-up.
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
1.16 Data Output and Noise Cancellation Filter
The data output pin DTAO delivers the demodulated data signal that can be further processed by a noise cancellation filter (NCF). The NCF can be disabled if pin CINT is connected to VEE. In this case the multiplexer (MUX) connects the receiver output DTAO directly to the data slicer output.
data slicer output
MUX
DTAO
Fig. 9:
NCF
CINT
Data output and noise filter
noise cancellation filter
CF3
The noise cancellation filter can suppress random pulses in the data output which are shorter than tmin.
CF3 = 15 10 -6 t min =
15 10 -6 7.5 10 -6 = RNRZ RRZ
The NCF can also operate as a muting circuit for RF input signals that are below sensitivity level if the bandwidth of the preceding data filter is selected much higher than the bandwidth of the NCF. This would be the case if no RF signal is present. In contrast to conventional muting (or squelch) circuits, this topology does not need the RSSI signal for level indication. The filtering process is done by means of an analogue integrator. The cut-off frequency of the NCF is set by the external capacitor connected to pin CINT. This capacitor CF3 should be set according to the maximum data rate. Below table provides some recommendations.. During receiver start-up a sequencer checks if pin CINT is connected to a capacitor or to ground. The maximum value of CF3 should not exceed 12nF. This defines the lowest data rate that can be processed if the noise cancellation filter is activated.
RRZ [kbit/s] 0.6 1.2 1.6 2.4 3.3 4.8 6.0
RNRZ [kbit/s] 1.2 2.4 3.2 4.8 6.6 9.6 12
CF3[nF] 12 6.8 4.7 3.3 2.2 1.5 1.2
In shutdown mode pin DTAO is set to Hi-Z state.
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 2
2.1
Functional Description
Frequency Planning
Because of the double conversion architecture that employs two mixers and two IF signals, there are four different combinations for injecting the LO1 and LO2 signals: * * * * LO1 high side and LO2 high side: LO1 high side and LO2 low side: LO1 low side and LO2 high side: LO1 low side and LO2 low side: receiving at fRF(high-high) receiving at fRF(high-low) receiving at fRF(low-high) receiving at fRF(low-low)
As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 10 shows this for the case of receiving at fRF(high-high). In the example of Fig. 10, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low). The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means either the upper or lower sideband of IF1 can be selected. In the example of Fig. 10, LO2 high-side injection has been chosen to select the IF2 signal resulting from fRF(high-high).
f LO2
f LO2
f RF
f RF
f LO1
f RF
f RF
Fig. 10: The four receiving frequencies in a double conversion superhet receiver It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO signal frequencies (fLO1 , fLO2) and the reference oscillator frequency fRO.
f LO1 = N 1 f LO2
f LO2 = N 2 f RO
The operating frequency of the internal IF filter (IFF) and FSK demodulator (FSK DEMOD) are 1.8MHz. Therefore the second IF (IF2) is set to 1.8MHz as well.
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
2.2 Calculation of Frequency Settings
The receiver has two predefined receive frequency plans which can be selected by the RFSEL control pin. Depending on the logic level of RFSEL pin the sideband selection of the second mixer and the counter settings for N1 and N2 are changed accordingly. RFSEL 0 1 Injection high-low low-high fRFmin [MHz] 300 610 fRFmax [MHz] 470 930 N1 4 2 N2 6 12
The following table shows the relationships of several internal receiver frequencies for the two input frequency ranges. fRF [MHz] 300 to 470 fIF1 fLO1 fLO2 fRO
f RF + N 1f IF2 N1 - 1 f RF - N 1f IF2 N1 + 1
N 1 (f RF + f IF2 ) N1 - 1 N 1 (f RF + f IF2 ) N1 + 1
f RF + f IF2 N1 - 1 f RF + f IF2 N1 + 1
f RF + f IF2 N 2 (N 1 - 1) f RF + f IF2 N 2 (N 1 + 1)
610 to 930
Given IF2 = 1.8MHz and the corresponding N1, N2 counter settings, above equations can be transferred into the following table. fRF [MHz] 300 to 470 610 to 930 fIF1 fLO1 fLO2 fRO
f RF + 7.2MHz 3 f RF - 3.6MHz 3
4(f RF + 1.8MHz ) 3 2(f RF + 1.8MHz ) 3
f RF + 1.8MHz 3
f RF + 1.8MHz 18 f RF + 1.8MHz 36
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
2.3 Standard Frequency Plans
fRF [MHz] 315 433.92 868.3 915 fIF1 [MHz] 107.40 147.04 288.23 303.80 fLO1 [MHz] 422.40 580.96 580.07 611.20 fLO2 [MHz] 105.60 145.24 290.03 305.60 fRO [MHz] 17.600000 24.206667 24.169444 25.466667
IF2 = 1.8MHz. RFSEL 0 1
2.4
433/868MHz Frequency Diversity
The receiver's multi-band functionality can be used to operate at two different frequency bands just by changing the logic level at pin RFSEL and without changing the crystal. This feature is applicable for common use of the 433 and 868MHz bands. Below table shows the corresponding frequency plans. IF2 = 1.8MHz. RFSEL 0 1 fRF [MHz] 433.25 868.3 fIF1 [MHz] 146.82 288.23 fLO1 [MHz] 580.07 580.07 fLO2 [MHz] 145.02 290.03 fRO [MHz] 24.169444
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 3
3
Pin Definitions and Descriptions
Pin No. Name LNAO1 I/O Type analog output
VCC 1k VEE
Functional Schematic
Vbias Vbias
Description LNA output 1
LNAO1 3
1
LNAI1
analog input
LNAI1 1
LNA input 1
VEE
2 4
VEE MIXP
ground analog input
MIXP
VCC 2k Vbias VCC 2k
negative supply voltage MIX1 positive input
MIXN 5
5
MIXN
analog input
4
MIX1 negative input
VEE
VEE
6
LNAO2
analog output
VCC
Vbias Vbias
LNAO2 6
VEE
LNA output 2
8
LNAI2
analog input
LNAI2 8
1k
LNA input 2
VEE
7 9 10 11 12 13 14
VEE VCC MIXO VEE IFAP IFAN MODSEL
ground supply analog output ground analog input analog input CMOS input
MODSEL
400
negative supply voltage positive supply voltage not used pin left open mixer 2 output negative supply voltage IF amplifier positive input not used pins left open
VCC VCC
IF amplifier negative input modulation select input
14
VEE VEE
39010 71121 Rev. 007
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Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
Pin No. 15
Name SLCSEL
I/O Type CMOS input
Functional Schematic
VCC VCC
Description slicer mode select input
SLCSEL
400
15
VEE VEE
VCC
16
DF2
analog I/O
DF2
VCC
data filter connection 2
400
16
100k
17
DF1
DF1
400
17
VEE
100k
analog I/O
VEE VCC
data filter connection 1
18
DFO
analog output
DFO
VCC
VCC
data filter output
400
18
VEE
19
SLC
SLC
400
100k
analog input
VCC
slicer reference input
100k 100k
19
VEE
20
PDP
analog output
PDP
VCC
VCC
peak detector positive output
400
20
VEE
21
PDN
analog output
PDN
VCC
peak detector negative output
400
21
VEE
39010 71121 Rev. 007
Page 17 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
Pin No. 22 23
Name VCC CINT
I/O Type supply analog input
Functional Schematic
Description positive supply voltage
VCC
capacitor for noise cancellation filter pin must be connected to ground if noise cancellation filter is not used
CINT 23
VEE
24
RSSI
analog output
RSSI
VCC
receive signal strength indication
400 51k VEE VEE
VCC 16k
24
25
ROI
analog input
VCC
reference oscillator input
ROI 25
VEE
VEE
26 27 28
TEST IFSEL CLKO
CMOS input CMOS input CMOS output
not used connect to ground not used connect pin to ground
VCC
test pin IF select input clock output connect pull-up resistor to activate clock
CLKO 28
VEE
29
DTAO
CMOS output
DTAO
VCC
VCC
data output
220
29
VEE
30
ENRX
CMOS input
ENRX
VCC
VCC
enable RX mode control
400 380k VEE VEE
30
39010 71121 Rev. 007
Page 18 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
Pin No. 31
Name RFSEL
I/O Type CMOS input
Functional Schematic
VCC VCC
Description receive frequency select input
RFSEL
400
31
VEE VEE
32
LNASEL
LNASEL
400
VEE
39010 71121 Rev. 007
Page 19 of 28
500k
32
500k
CMOS input
VCC
LNA select input
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 4
4.1
Technical Data
Absolute Maximum Ratings
Parameter Symbol VCC VIN TSTG TJ RthJA Pdiss VESD HBM according to MIL STD 833D, method 3015.7 1 Condition Min 0 -0.3 -55 Max 7 VCC +0.3 150 150 22 0.12 Unit V V C C K/W W kV
Operation beyond absolute maximum ratings may cause permanent damage of the device.
Supply voltage Input voltage Storage temperature Junction temperature Thermal Resistance Power dissipation Electrostatic discharge
4.2
Normal Operating Conditions
Parameter Symbol VCC TA VIL VIH fRF fIF1 fLO1 fLO2 fREF fCLK f RASK RFSK bi-phase code NRZ bi-phase code NRZ Condition Min 2.1 -40 ENRX, SEL pins ENRX, SEL pins RFSEL=0 RFSEL=1 RFSEL=0 RFSEL=1 fLO1 = 24*fREF RFSEL=0, fLO2 = fLO1 / 4 RFSEL=1, fLO2 = fLO1 / 2 set by the crystal fCLK = fREF / 8 0.7*VCC 300 610 100 200 400 100 200 16 2.0 10 Max 5.5 125 0.3*VCC 470 930 170 310 640 160 320 27 3.375 100 50 100 50 100 Unit V C V V MHz MHz MHz MHz MHz MHz kHz kbps
Supply voltage Operating temperature Input low voltage (CMOS) Input high voltage (CMOS) Input frequency range First IF range LO1 range (VCO frequency) LO2 range XOSC frequency CLKO frequency FSK deviation Data rate ASK Data rate FSK
39010 71121 Rev. 007
Page 20 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
4.3 DC Characteristics
all parameters under normal operating conditions, unless otherwise stated; typical values at TA= 23 C and VCC = 3 V, all parameters based on test circuits as shown Fig. 11 to Fig. 12 Parameter Operating Currents Shutdown current Supply current reference oscillator Supply current, FSK ISDN IRO IFSK ENRX=0, TA = 85C ENRX=0, TA = 125C ENRX=1, t < tonRO ENRX=1, MODSEL=1 SLCSEL=0 LNASEL=0 or 1 ENRX= 1, MODSEL= 0 SLCSEL=0 LNASEL=0 or 1 ENRX, SEL pins ENRX, SEL pins ENRX=1 ENRX=0 SEL pins SEL pins ENRX=1 ENRX=1 DTAO pin, ISINK = 600A DTAO pin, ISOURCE = 600A 0.7*VCC 0.9*VCC 0.7*VCC 2 8 30 1 1 1 0.1*VCC 1.5 10.2 50 200 4 nA A mA mA Symbol Condition Min Typ Max Unit
Supply current, ASK
IASK
9.8
mA
Digital Pin Characteristics (except of LNASEL) Input low voltage (CMOS) Input high voltage (CMOS) Pull down current ENRX pin Low level input current ENRX pin High level input current Low level input current LNASEL Pin Characteristics Input voltage LNA1 active Input voltage LNA2 active DTAO Pin Characteristics Output low voltage Output high voltage VOL VOH 0.3*VCC V V VLNASEL1 VLNASEL2 V V VIL VIH IPDEN IINLEN IINHSEL IINLSEL 0.3*VCC V V A A A A
39010 71121 Rev. 007
Page 21 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
4.4 AC System Characteristics
all parameters under normal operating conditions, unless otherwise stated; typical values at TA= 23 C and VCC = 3 V, all parameters based on test circuits as shown Fig. 11 Parameter Receive Characteristics Input Sensitivity 1)
315MHz 433MHz 868MHz 915MHz 315MHz 433MHz 868MHz 915MHz
Symbol
Condition MODSEL RFSEL 0 1 1 0 0 1 MODSEL=1 MODSEL=0, M>20dB w/o SAW filter
Min
Typ
Max
Unit
FSK
ASK
Pmin1 Pmin2 Pmin3 Pmin4 Pmin5 Pmin6 Pmin7 Pmin8 Pmax, FSK Pmax, ASK Pspur IR1 IR2 GLNA
-107 -107 -104 -102 -112 -112 -108 -105 -10 -10 -54 20 25
dBm
dBm
Maximum input signal - FSK Maximum input signal - ASK Spurious emission Image rejection 1st IF Image rejection 2nd IF LNA Parameters Voltage gain IF Filter Parameters Center frequency 3dB bandwidth 40dB bandwidth IF Amplifier / RSSI Operating frequency RSSI dynamic range RSSI slope FSK Demodulator Input frequency range Carrier acceptance range Demodulator sensitivity
dBm dBm dBm dB dB
depends on external LC tank
18
dB
fcent B3dB B40dB fIFA DRRSSI SRSSI fDEM fDEM SDEM 0.4
1.8 300 1.4 11 60 20 1.8 80 5
MHz kHz MHz MHz dB mV/dB MHz kHz mV/ kHz
1) at 4kbps NRZ, BER 310-3, peak detector data slicer, LNASEL = 0 or 1
39010 71121 Rev. 007
Page 22 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
Parameter Baseband Data Path Data filter bandwidth Peak detector load current Start-up Parameters Reference oscillator start-up time Sequencer time Receiver start-up time Frequency Stability Frequency pulling by supply voltage
Symbol BDF IPKD
Condition depending on CF1, CF2
Min
Typ
Max 100
Unit kHz A
500 depending on crystal parameters 5504 / fREF tonRO + tSEQ
tonRO tSEQ tonRX
350 200 250 0.6
650 350 1
s s ms
dfVCC
3
ppm/V
4.5
External Components
Parameter Symbol f0 CL C0 R1 CF3 RCL CL Condition fundamental mode, AT Min 16 10 Max 27 15 5 60 12 600 50 Unit MHz pF pF nF pF
Crystal Parameters Crystal frequency Load capacitance Static capacitance Series resistance Noise Cancellation Filter Integrator capacitor Clock Output Pull-up resistor Load capacitance depends on data rate
39010 71121 Rev. 007
Page 23 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 5
5.1
Test Circuits
Dual-Channel Application Circuit
* * for antenna-diversity applications for frequency-diversity applications
output
LNASEL RFSEL ENRX CLKO
FSK ASK
VCC
RCL
XTAL CX
RSSI
RFSEL 31
32
ENRX 30
DTAO 29
CLKO 28
IFSEL 27
TEST 26
ROI 25
50
L1 L2 CB3 C4
VCC
C3
CRS CF3 CP2 CP1 CB2
1 LNAI1 2 VEE
RSSI 24 CINT 23 VCC 22
C5
3 LNAO1 4 MIXP 5 MIXN
MLX71121
32L QFN 5x5
MODSEL SLCSEL
PDN 21 PDP 20 SLC 19 DFO 18 DF2 DF1 17
C6
6 LNAO2 7 VEE
L3
50
C9
9
10
11
12
13
IFAN
IFAP
VCC
VEE
8
MIXO
LNAI2
CF1
14
15
16
CB1
FSK ASK
VCC
CF2
CB0
Fig. 11: Dual-channel circuit schematic, peak detectors activated
39010 71121 Rev. 007
Page 24 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver
5.1.1 Test Circuit Component List of Figures 11
Value @ 315 MHz
100 pF 4.7 pF 100 pF 100 pF 100 pF 33 nF 330 pF 330 pF 330 pF 680 pF 330 pF
Part
C3 C4 C5 C6 C9 CB0 CB1 CB2 CB3 CF1 CF2 CF3 CP1 CP2 CRS CSL CX L1 L2 L3 RCL XTAL
Size
0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SMD 5x3.2
Value @ Value @ 433.92 MHz 868.3 MHz
100 pF 3.9 pF 100 pF 100 pF 100 pF 33 nF 330 pF 330 pF 330 pF 680 pF 330 pF 100 pF 2.2 pF 100 pF 100 pF 100 pF 33 nF 330 pF 330 pF 330 pF 680 pF 330 pF
Value @ 915 MHz
100 pF 1.5 pF 100 pF 100 pF 100 pF 33 nF 330 pF 330 pF 330 pF 680 pF 330 pF
Tol.
5% 5% 5% 5% 5%
Description
LNA input filtering capacitor LNA output tank capacitor MIX1 positive input matching capacitor MIX1 negative input matching capacitor LNA input filtering capacitor
10% decoupling capacitor 10% decoupling capacitor 10% decoupling capacitor 10% decoupling capacitor 10% 10% 10% data low-pass filter capacitor, for data rate of 4 kbps NRZ data low-pass filter capacitor, for data rate of 4 kbps NRZ optional capacitor for noise cancellation filter positive PKDET capacitor, for data rate of 4 kbps NRZ negative PKDET capacitor, for data rate of 4 kbps NRZ RSSI output low pass capacitor, for data rate of 4 kbps NRZ data slicer capacitor, for data rate of 4 kbps NRZ crystal series capacitor matching inductor LNA output tank inductor matching inductor optional CLK output resistor, to clock output signal generated fundamental-mode crystal from Telcona, or equivalent part
value according to the data rate connected to ground if noise filter not used 33 nF 33 nF 1 nF 100 nF 27 pF 56 nH 27 nH 56 nH 3.3 k 17.60000 MHz 33 nF 33 nF 1 nF 100 nF 27 pF 27 nH 15 nH 27 nH 3.3 k 24.206667 MHz 33 nF 33 nF 1 nF 100 nF 12 pF 0 3.9 nH 0 3.3 k 24.169444 MHz 33 nF 33 nF 1 nF 100 nF 12 pF 0 3.9 nH 0 3.3 k 25.46667 MHz
10% 10% 10% 10% 5% 5% 5% 5% 5%
for averaging detection mode only
20ppm cal., 30ppm temp.
Note:
NIP - not in place, may be used optionally
39010 71121 Rev. 007
Page 25 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 6 Package Description
The device MLX71121 is RoHS compliant.
D 24 25 17 16
A3
E
32 1 e 8 b
9 A1 A
exp osed pad
E2
L D2
The "exposed pad" is not connected to internal ground, it should not be connected to the PCB.
Fig 13: all Dimension in mm D
min max min max 4.75 5.25 0.187 0.207
32L QFN 5x5 Quad
E
4.75 5.25 0.187 0.207
D2
3.00 3.25 0.118 0.128
E2
3.00 3.25 0.118 0.128
A
0.80 1.00 0.0315 0.0393
A1
0 0.05 0 0.002
A3
0.20
L
0.3 0.5 0.0118 0.0197
e
0.50
b
0.18 0.30 0.0071 0.0118
all Dimension in inch
0.0079 0.0197
6.1
Soldering Information
* The device MLX71121 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20 Page 26 of 28 Data Sheet Feb/08
39010 71121 Rev. 007
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 7 Reliability Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: Reflow Soldering SMD's (Surface Mount Devices) * * IPC/JEDEC J-STD-020 "Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2)" EIA/JEDEC JESD22-A113 "Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2)"
Wave Soldering SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * * EN60749-20 "Resistance of plastic- encapsulated SMD's to combined effect of moisture and soldering heat" EIA/JEDEC JESD22-B106 and EN60749-15 "Resistance to soldering temperature for through-hole mounted devices"
Iron Soldering THD's (Through Hole Devices) * EN60749-15 "Resistance to soldering temperature for through-hole mounted devices"
Solderability SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * EIA/JEDEC JESD22-B102 and EN60749-21 "Solderability"
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.aspx
8 ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39010 71121 Rev. 007
Page 27 of 28
Data Sheet Feb/08
MLX71121
300 to 930MHz FSK/FM/ASK Receiver 9 Disclaimer
1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided 'as is'. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. (c) Melexis NV. All rights reserved.
For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct: Europe, Africa:
Phone: +32 1367 0495 E-mail: sales_europe@melexis.com
Americas:
Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com
Asia:
Phone: +32 1367 0495 E-mail: sales_asia@melexis.com
ISO/TS 16949 and ISO14001 Certified 39010 71121 Rev. 007 Page 28 of 28 Data Sheet Feb/08

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